1. Field of the Invention
The present invention relates to a field effect semiconductor device and a manufacturing method thereof and more particularly to an improvement for increasing anti-breakdown ability thereof.
2. Description of Prior Arts
FIG. 10A is a plan view schematically showing the surface part of a conventional n-channel power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100, and FIG. 10B is a cross-sectional view taken along the line B1--B1 of FIG. 1OA. FIG. 10A corresponds to a plan view taken on the plane B3--B3 of FIG. 10B.
The MOSFET 100 comprises n.sup.- -type layers 3a and 3b formed on a p-type silicon substrate 1. An n.sup.+ -type buried layer 2 is provided between the substrate I and the n.sup.- -type layer 3b. The n.sup.- -type layer 3b functions as an n.sup.- -type drain layer. An n.sup.+ -type drain region 4 is formed between the n.sup.- -type layers 3a and 3b. As is apparent from FIG. 10A, the n.sup.+ -type drain region 4 surrounds the n.sup.- -type layer 3b, and the combination of the n.sup.+ -type drain region 4 and the n.sup.- -type drain layer 3b forms the drain region of the MOSFET.
In the n.sup.- -type layer 3b, two p-type semiconductor regions 5 are formed. In each of the p-type semiconductor regions 5 is provided an n.sup.+ -type source region 6 having a hole in the center thereof. The portions of the p-type semiconductor regions 5 which surround the n.sup.+ -type source regions 6 are channel forming regions 9.
A gate insulating film 7 is formed so as to cover the surface of the n.sup.- -type layer 3b and parts of the n.sup.+ -type source regions 6. A gate electrode 8 opposite to the channel forming regions 9 and peripheral regions thereof is formed on the gate insulating film 7 A source electrode 10 is provided so that the n.sup.+ -type source regions 6 and the p-type semiconductor regions 5 are short-circuited to each other. A layer insulating film 11 insulates the gate electrode 8 and the source electrode 10 electrically from each other. A drain electrode 12 is formed on the n.sup.+ -type drain region 4. A back electrode 13 connected to the ground level is formed on the bottom major surface of the semiconductor substrate I. As is clear from FIGS. 10A and 10B, the MOSFET 100 is an up drain type MOSFET comprising two MOS unit cells connected in parallel and being provided with the gate electrode 8 and the drain electrode 12 on the top surface side of the MOSFET or semiconductor element 100.
In the MOSFET having such structure, a gate voltage is applied between the gate electrode 8 and the source electrode 10 under the conditions that a drain voltage is applied between the drain electrode 12 and the source electrode 10. Thus, channels are formed in the channel forming regions 9, and current flows through these channels between the drain electrode 12 and the source electrode The magnitude of this current can be controlled by the magnitude of the gate voltage.
For such operations, it is necessary to keep the potential of the n.sup.+ -type source regions 6 and the potential of the center portions of the p-type semiconductor regions 5 equal at a same level. This is because the relation between the gate voltage and the channel current becomes indefinite when the p-type semiconductor regions 5 are at electrical floating levels from the n.sup.+ -type source regions 6. For satisfying such conditions, the source electrode 10 is formed so that the n.sup.+ -type source regions 6 and the center portions of the p-type semiconductor regions 5 are short-circuited to each other.
The output characteristics of the MOSFET 100 are shown in FIG. 11. When a source-drain voltage V.sub.D is lower than a breakdown voltage V.sub.BD, a source-drain current I.sub.D increases as a function of a gate voltage V.sub.G. When the source-drain voltage V.sub.D reaches the breakdown voltage V.sub.BD, the MOSFET 100 is broken down instantaneously. Referring to FIG. 12 corresponding to a cross-sectional view taken along the line B2--B2 of FIG. 9A and FIG. 13 corresponding to a partially enlarged view thereof, this breakdown phenomenon in the MOSFET 100 is analized in detail hereinafter.
Considered is the case where the drain voltage V.sub.D applied between the source electrode 10 and the drain electrode 12 is increased in FIG. 12. When the drain voltage V.sub.D reaches the breakdown voltage V.sub.BD between the n.sup.- -type drain layer 3b and the p-type semiconductor region 5, a breakdown current J.sub.C indicated by arrows flows from the n.sup.- -type drain layer 3b to the source electrode 10.
An equivalent circuit of the MOS unit cells in such a state, as is shown in FIG. 13, comprises a reverse parallel connection between a parasitic npn transistor T.sub.r having a base resistor R.sub.a and a diode D.sub.a. In the breakdown state, the breakdown current J.sub.C of FIG. 12 flowing into the bottom of the n.sup.+ -type source region 6 is directed through the base resistor R.sub.a of the transistor T.sub.r to the source electrode 10. The parasitic transistor T.sub.r is allowed to conduct, when the magnitude of the breakdown current J.sub.C satisfies the following formula (I): EQU J.sub.C .times.R.sub.a &gt;0.6[V] (1)
where "0.6 [V]" is a built-in voltage of a pn-junction using silicon. The conduction of the parasitic transistor T.sub.r causes the respective MOS unit cells to be in a blocking state. As a result, the MOSFET 100 is broken down in a short time. For improving the anti-breakdown ability of this type of semiconductor device, it is necessary to prevent the product (J.sub.C .times.R.sub.a) in the breakdown state from increasing.
However, in the conventional device structure, since the product (J.sub.C .times.R.sub.a) exceeds 0.6 [V] as soon as the drain voltage reaches the breakdown voltage V.sub.BD, the anti-breakdown ability thereof is not increased so much. This is a problem not only for the power MOSFETs but also for other field effect semiconductor devices such as IGBTs.